1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a non-volatile memory.
2. Description of the Related Art
Memory is a semiconductor device for storing data or programs. As the functional capability of the microprocessor inside a computer becomes more powerful, the programs that can be run by software are growing larger and so more memory is demanded. To fabricate larger capacity and inexpensive memory to meet the demands, innovation techniques and processes for fabricating memory devices are sought. In fact, it has become the driving power for increasing the level of integration in semiconductor production.
Among various types of memory products, non-volatile memory is a type of memory whose stored data can be programmed, read and erase multiples of times. Furthermore, the stored data is retained even when the power to the device has been turn off. Hence, non-volatile memory is a memory device that has been widely adopted inside personal computer and electronic equipment.
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for fabricating a conventional non-volatile memory device. First, as shown in FIG. 1A, a substrate 100 is provided. The substrate 100 has a memory cell region 101 and a peripheral circuit region 103. A tunneling dielectric layer 102, a charge-trapping layer 104, a barrier dielectric layer 105, a pad conductive layer 110, a conductive layer 112 and a patterned cap layer 114 have already formed over the substrate 100 on the memory cell region 101. Furthermore, a gate oxide layer 108, a conductive layer 112 and a patterned cap layer 114 have already formed over the substrate 100 on the peripheral circuit region 103. Then, the conductive layer 112 and the pad conductive layer 110 are defined using the patterned cap layer 114. Therefore, a plurality of stacked gate structures 116 is formed on the memory cell region 101 and a plurality of stacked gate structures 116a is formed on the peripheral circuit region 103.
As shown in FIG. 1B, a plurality of dielectric layers 117 is formed on the sidewalls of the stacked gate structures 116 and 116a. Then, a conductive layer (not shown) is formed over the substrate 100. Thereafter, a portion of the conductive layer is removed to expose the surface of the stacked gate structures 116 and the stacked structures 116a. Thus, a plurality of gates 118 are formed between neighboring stacked gate structures 116 to produce a memory cell row 120. A plurality of conductive spacers 122 is also formed on the sidewalls of the stacked gate structures 116 and 116a. 
As shown in FIG. 2C, the barrier dielectric layer 106, the charge-trapping layer 104 and the tunneling dielectric layer 102 not covered by the memory cell row 120 and the gate oxide layer 108 not covered by the stacked gate structures 116a are removed. Thereafter, a plurality of source/drain regions 124 is formed in the substrate 100 on the respective sides of the stacked gate structures 116 and 116a. 
In FIG. 1B of the foregoing process, the spacers between two neighboring stacked gate structures 116 are used to form another stacked gate structure 118 on the memory cell region 101 for increasing the level of integration of the devices. However, in the process of forming the stacked gate structure 118 on the memory cell region 101, conductive spacers 122 are also formed on the sidewalls of the stacked gate structures 116a on the peripheral circuit region 103. Hence, an additional process must be carried out to remove the conductive spacers 122, thereby complicating the production process and increasing the production cost.